1. Field of the Invention
The present invention relates to a correlator and, more particularly, to a correlator which is used for synchronization acquisition and realizes low current consumption.
2. Description of the Prior Art
Recently, mobile communication systems such as a system using portable telephones have become widespread. One of the communication schemes used by such mobile communication systems is CDMA (Code Division Multiple Access).
According to CDMA, on the transmitting side, data is spread by using one of predetermined spreading codes which differ depending on the data to be transmitted, and the spread data is transmitted. On the receiving side, the data is obtained by spreading (so-called despreading) the reception signal by using a spreading code identical to the one used on the transmitting side (to be precise, a code complex conjugate to the spreading code on the transmitting side).
In communication by such CDMA, it is very important to establish synchronization between a terminal station and a base station. A period of time corresponding to the lowest common denominator of the period of a spreading code used in the downlink direction (in which the base station transmits, and the terminal station receives) is required for the terminal station to start synchronization acquisition operation and establish synchronization with the base station. In general, an enormous period of time is required.
Of downlink spreading codes used in W-CDMA (Wide Band CDMA) in the process of being standardized in ARIB (Association of Radio Industries and Businesses) is designed such that some codes with long periods are replaced with spreading codes with shorter periods so as to simplify the above initial synchronization establishment process in the terminal station.
Although such a spreading code has a relatively short period, even this short-period spreading code requires correlation computation corresponding to a certain length (e.g., 256 chips).
As methods of performing correlation computation for such synchronization acquisition, a method using a matched filter and a method using a sliding correlator are available. These two methods will be described below.
FIG. 1 is a block diagram showing the arrangement of a matched filter used as a correlator according to the first prior art.
Referring to FIG. 1, input signals 100 are sequentially input to a tapped shift register 10. The shift register 10 is long enough to store input signals corresponding to a 1-symbol time (generally corresponding to one period of the above short-period spreading code).
In this case, n despreading phase points are contained in a 1-symbol time, and multipliers 21 to 2n respectively multiply signals 101 to 10n output from the respective taps of the shift register 10 and despreading codes Cn to C1 to output the resultant data as multiplication results 201 to 20n. An adder 30 adds the multiplication results 201 to 20n to obtain a despreading result 300.
In the method using this matched filter, since despreading is performed with respect to one phase point every time an input signal corresponding to one sample is input, despreading results with respect to all the phase points can be obtained at high speed. However, this operation consumes a large amount of current for the following reason.
In general, an input signal is a multilevel signal and often handled as a complex signal expressed by I and Q components. This makes it necessary for the shift register 10 to always operate at high speed. The shift register 10 therefore consumes a very large amount of current.
The adder 30 also consumes a large amount of current. This point will be described with reference to FIG. 2.
FIG. 2 shows an example of the internal arrangement of the adder 30 in FIG. 1.
For the sake of simplicity, FIG. 2 shows a case wherein the number of input signals to the adder 30, i.e., the number of taps of the shift register 10, is eight.
As shown in FIG. 2, the adder 30 is comprised of a plurality of adders each for adding two inputs, and outputs the despreading result 300 as a result. Since the adder 30 has such a large-scale arrangement and always operates at high speed, a large amount of current is consumed.
FIG. 3 shows the method using the sliding correlator as the second prior art.
FIG. 3 is a block diagram showing the arrangement of the sliding correlator.
Referring to FIG. 3, a despreading code generator 70 generates a despreading code Ci, and a multiplier 40 multiplies this despreading code Ci by an input signal 100 to obtain a signal 110. In addition, an adder 50 and register 60 integrate the signals 110 corresponding to a 1-symbol time. When the signals corresponding to a 1-symbol time are integrated, a register output 130 becomes a despreading result 130 corresponding to one phase point. Therefore, it takes a period of time corresponding to n periods of a despreading code to complete despreading with respect to all the phase points by using this sliding correlator.
Although the current consumption, which poses a problem in the above correlator using the matched filter, can be considerably reduced by using this sliding correlator, a long processing time is required.
As the third prior art, therefore, an arrangement having a plurality of sliding correlators each having the same arrangement as that shown in FIG. 3 (n sliding correlators are required for a despreading time equivalent to that required for the matched filter) may be used.
According to this example, by concurrently operating a plurality of sliding correlators, the processing time required to obtain despreading results corresponding to all the phase points can be shortened to a time equivalent to that required when the matched filter is used.
In this example of concurrently operating the plurality of sliding correlators, however, the processing time is shortened at the expense of current consumption. Although the current consumption can be reduced as compared with the correlator using the matched filter, a problem is left unsolved in terms of current consumption.
As the fourth prior art, the method described in Chin and Furukawa, xe2x80x9cLow Power Consumption Design of Wide Band DS-CDMA Digital Matched Filterxe2x80x9d (The 11th Circuit and System (Karuizawa) Workshop: on Apr. 20-21, 1998) is available.
FIG. 4 is a block diagram showing the arrangement of a correlator proposed in xe2x80x9cLow Power Consumption Design of Wide Band DS-CDMA Digital Matched Filterxe2x80x9d.
Referring to FIG. 4, reference symbol FFs denotes a register for storing received input spread data; and C, a multiplier for multiplying data from the register FFs by a despreading code. A DMF output indicates an output from this proposed DMF, i.e., a digital matched filter.
The fourth prior art is implemented by shifting a despreading code instead of shifting an input signal by using a shift register. According to the fourth prior art, the current consumption, which poses a problem in the conventional method using the matched filter, can be reduced.
The method using the matched filter has been described as the first prior art; the method using the sliding correlator, as the second prior; the method of concurrently operating the n sliding correlators, as the third prior art; and the method of shifting a despreading code instead of an input signal, as the fourth prior art. In the first prior art, a large amount of current is consumed. In the second prior art, a long processing time is required.
According to the third and fourth prior arts, no problem arises in terms of processing time, and the current consumption can be reduced as compared with the conventional method using the matched filter.
Recently, however, demands have arisen for smaller batteries in accordance with a tendency towards smaller portable telephones. In addition, demands have arisen for portable telephones that consume less current, in order to allow operation for a longer period of time without changing the battery size.
The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide a correlator which can realize lower current consumption than a conventional correlator without decreasing the operation speed.
In order to achieve the above object, according to the first aspect of the present invention, there is provided a correlator which performs synchronization acquisition by sequentially despreading a spread modulated signal at a plurality of synchronization point candidates, and can stop correlation computation on the basis of the value of a despreading code.
According to the second aspect of the present invention, there is provided a correlator for performing synchronization acquisition by despreading a spread modulated signal having undergone spread spectrum modulation, wherein the spread spectrum modulation is performed by BPSK or QPSK, and despreading is performed according to one of equations given below:                     ∑                  i          =          0                          n          -          1                    ⁢              xe2x80x83            ⁢              C        ⁢                  xe2x80x83                ⁢                              (            i            )                    ·          D                ⁢                  xe2x80x83                ⁢                  (          i          )                      =                                                      ∑                              i                =                0                                            n                -                1                                      ⁢                          xe2x80x83                        ⁢                          D              ⁢                              xe2x80x83                            ⁢                              (                i                )                                              -                      2            ⁢                                          ∑                                  i                  =                  0                                                  n                  -                  1                                            ⁢                              xe2x80x83                            ⁢                              D                ⁢                                  xe2x80x83                                ⁢                                  (                  i                  )                                                                    ⁢                  ❘                                    C              ⁢                              xe2x80x83                            ⁢                              (                i                )                                      =                          -              1                                      ⁢                  
                ⁢                              ∑                          i              =              0                                      n              -              1                                ⁢                      xe2x80x83                    ⁢                      C            ⁢                          xe2x80x83                        ⁢                                          (                i                )                            ·              D                        ⁢                          xe2x80x83                        ⁢                          (              i              )                                          =                                    -                                          ∑                                  i                  =                  0                                                  n                  -                  1                                            ⁢                              xe2x80x83                            ⁢                              D                ⁢                                  xe2x80x83                                ⁢                                  (                  i                  )                                                              +                      2            ⁢                                          ∑                                  i                  =                  0                                                  n                  -                  1                                            ⁢                              xe2x80x83                            ⁢                              D                ⁢                                  xe2x80x83                                ⁢                                  (                  i                  )                                                                    ⁢                  ❘                                    C              ⁢                              xe2x80x83                            ⁢                              (                i                )                                      =            1                          ⁢                  xe2x80x83                ⁢        and                                ∑                  i          =          0                          n          -          1                    ⁢              xe2x80x83            ⁢              C        ⁢                  xe2x80x83                ⁢                              (            i            )                    ·          D                ⁢                  xe2x80x83                ⁢                  (          i          )                      =                  {                              ∑                          i              =              0                                      n              -              1                                ⁢                      xe2x80x83                    ⁢                      D            ⁢                          xe2x80x83                        ⁢                          (              i              )                                      }            +              {                              -                                          ∑                                  i                  =                  0                                                  n                  -                  1                                            ⁢                              xe2x80x83                            ⁢                              D                ⁢                                  xe2x80x83                                ⁢                                  (                  i                  )                                                              ⁢                      ❘                                                            C                  ⁢                                      xe2x80x83                                    ⁢                                      (                    i                    )                                                  ≠                1                            ,              1                                ⁢                                    +                              (                                                                            -                      j                                        ·                                                                  ∑                                                  i                          =                          0                                                                          n                          -                          1                                                                    ⁢                                              xe2x80x83                                            ⁢                                              D                        ⁢                                                  xe2x80x83                                                ⁢                                                  (                          i                          )                                                                                                      ⁢                                      ❘                                                                                            C                          ⁢                                                      xe2x80x83                                                    ⁢                                                      (                            i                            )                                                                          =                        1                                            ,                                              -                        1                                                                                            )                                      +                          (                                                j                  ·                                                            ∑                                              i                        =                        0                                                                    n                        -                        1                                                              ⁢                                          xe2x80x83                                        ⁢                                          D                      ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                                                            ⁢                                  ❘                                                                                    C                        ⁢                                                  xe2x80x83                                                ⁢                                                  (                          i                          )                                                                    =                                              -                        1                                                              ,                    1                                                              )                        +                          (                                                -                                                            ∑                                              i                        =                        0                                                                    n                        -                        1                                                              ⁢                                          xe2x80x83                                        ⁢                                          D                      ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                                                            ⁢                                  ❘                                                                                    C                        ⁢                                                  xe2x80x83                                                ⁢                                                  (                          i                          )                                                                    =                                              -                        1                                                              ,                                          -                      1                                                                                  )                                      }            
where n is the number of despreading phase points contained in a 1-symbol time, C(i) is the despreading code, and D(i) is the signal having undergone the spread spectrum modulation.
As is obvious from the above aspects, according to the present invention, there is provided a correlator which can realize performance equivalent to that of an arrangement designed to concurrently operate n conventional sliding correlators, each shown in FIG. 3, with about xc2xd the current consumption of the arrangement, when a spreading ratio n is sufficiently high, and spreading/despreading is performed by BPSK.
When the correlator of the present invention is compared with the conventional correlators, the current consumption increases in the order of the second prior art, the present invention, the fourth prior art, third prior art, and first prior art. With regard to the processing time, the present invention and the first, third, and fourth priors are equal, and the second prior art requires the longest processing time. That is, the present invention can realize lower current consumption than the prior arts without decreasing the operation speed.
In other words, according to the present invention, there is provided a correlator which decreases the operation ratio of a section which operates in accordance with a despreading code pattern to xc2xd that of a conventional scheme (when spreading is performed by BPSK) in despreading a spread modulated signal, and decreases the current consumption to about xc2xd that of the conventional scheme (when spreading is performed by BPSK) in a case of a sufficiently high spreading ratio by using a common total adder which operates regardless of the despreading code pattern.